Circuit Simulation and DFY

Circuit Design and Process Interface

Semiconductor Process Development

Parallel SPICE Simulator – NanoSpice™

Introduction

NanoSpice™ is a new generation high-capacity, high-performance parallel SPICE simulator, designed for the toughest simulation jobs, such as large post-layout analog circuit simulations that require capacity, speed and accuracy simultaneously. With its superior parallelization technologies, NanoSpice handles generic circuit simulation with 50M+ elements circuit size, an incomparable advantage no other SPICE simulator has, and delivers better performance as compared to other parallel SPICE simulators for large simulation jobs. NanoSpice also has an innovative, efficient and cost-effective parallelization license model.

Key Benefits

Highest accuracy: pure SPICE engine matching industry's highest accuracy standard
5X+ larger capacity: 50M+ element circuit capacity for generic circuit types
Fastest parallel SPICE: faster than other parallel SPICE simulators
Drop-in replacement: standard input/output formats and full compatible SPICE analysis features
Foundry validated accuracy: 16/14/10nm FinFET and 28nm FD-SOI ready

Applications

Analog (ADC, PLL, PMIC) and I/O (SerDes)
Memory characterization and verification (DRM, SRAM, flash, etc)
Custom digital, standard cell  
Library characterization

Design Flow Integration

Drop-in replacement of any SPICE simulator in existing design flows for any transistor-level circuit simulations
Plug and run without any special options

Model Support

Supports all public domain models, user-defined models and Verilog-A
BSIM3, BSIM4, BSIM6, BSIMSOI, BSIM-CMG, BSIM-IMG, UTSOI, PSP, HSIM2, HiSIM_HV, MOS9, MOS11
Gummel-Poon, VBIC, HICUM, Mextram
Diode, JFET, MESFET, RLC, TFT, TSMC model interface (TMI)

Specifications

Supports Hspice and Spectre netlist formats
Supports standard output formats for data analysis: FSDB, PSFASCII, SPICEASCII, ASCII, etc
Full SPICE analysis features: OP, DC, AC, Noise, Tran, Info, Sweep, Alter, Monte Carlo, PVT, Tran Noise, etc
Supports Verilog-A and behavioral sources
Supports VEC and VCD stimulus files
Supports SPEF back-annotation
Supports IBIS model, S-parameter and transmission line, etc
Drop-in replacement of any SPICE simulator in existing design flows

Platform Supported:

Redhat Enterprise V4, 5
CentOS V4, 5, 6

Download Datasheet